|As a static circuit checking program that operates on the
output of the circuit extractor, this program analyzes a layout in
terms of transistors and nodes. It identifies and classifies types
of transistors and nodes, and highlights unrecognized or incorrectly
connected elements. Threshold drop errors and pullup/pulldown ratio
errors are identified.
- Detect often overlooked electrical rules violations
- Violations and inconsistencies labeled on physical layout and
|The Phase Three Logic Electrical Rules Checker provides
fast, convenient means of detecting layout errors.
The Phase Three Logic Electrical Rules Checker performs a static
check of a MOS circuit. It classifies the types of transistors and
nodes in the circuit and highlights unrecognized or incorrectly
connected circuit elements. It also identifies electrical rules
violations such as multiple pullup transistors, incomplete signal
paths, too many threshold drops, pullup/pulldown ratio errors, and
propagation errors. The Electrical Rules Checker offers a convenient
method of detecting easily overlooked electrical errors in your
design before you attempt to simulate the circuit.
You can run the Electrical Rules Checker on a netlist file that you
have obtained from a physical layout or from a schematic. It is
generally used, however, to verify circuits extracted from a
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